1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to the technique of lowering power consumption in a static random access memory (SRAM).
2. Description of the Background Art
In accordance with the reduction in power consumption of electrical equipment in these years, there have been intensive efforts to reduce power consumption of semiconductor memory devices employed in such electronic equipment.
As one method of partially achieving low power consumption of semiconductor memory devices, Japanese Patent Laying-Open No. 7-161192 discloses the provision of a first transfer gate between a bit line pair and a sense amplifier to prevent full swing of the potential of the bit line pair isolated from the first transfer gate.
In an SRAM having the memory cell array divided into a plurality of blocks, the global bit line connecting respective blocks of memory cells still attains a full swing even though the potential amplitude of the bit line is restricted to a partial swing as described above. Power consumption is particularly noticeable when there are many output terminals.